The present invention relates to reducing line width roughness (LWR) of a feature of an etch layer. More specifically, the present invention relates to a plasma pre-etch treatment of a patterned photoresist mask through which a feature is to be etched in an underlying etch layer.
During semiconductor wafer processing, features of the semiconductor device are defined in the wafer using well-known patterning and etching processes. In these processes (photolithography), a photoresist (PR) material may be deposited on the wafer and then is exposed to light filtered by a reticle. The reticle may be a transparent plate that is patterned with exemplary feature geometries that block light from propagating through the reticle.
After passing through the reticle, the light contacts the surface of the photoresist material. The light changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material, resulting in a patterned photoresist mask. In the case of positive photoresist materials, the exposed regions are removed, and in the case of negative photoresist materials, the unexposed regions are removed. Thereafter, the wafer is etched to remove the underlying material from the areas that are no longer protected by the patterned photoresist mask, and thereby produce the desired features in the wafer.
As the critical dimensions (CDs) of semiconductor integrated circuitry features shrinks below 45 nm, the control of photoresist mask layers for line and space features with conventional photolithography process is reaching its limits. Poor and distorted line edges, as well as incompletely developed residue of photoresist layer will cause significant roughness at the edges of line and space features causing line edge roughness (LER) and variation in the CD of the line and space features, i.e., line width roughness (LWR). This non-uniform edge pattern will be transferred and/or amplified during multiple etch process steps that are required for semiconductor device fabrication, causing degradation of device performance and yield loss.
The ideal feature has an edge that is “straight like a ruler” as shown in FIG. 1A, when viewed from top down. However, for various reasons as described above, the actual line feature may appear jagged and have line width roughness (LWR). The LWR includes a low-frequency roughness, such as a wiggling (as shown in FIG. 1B), and a high-frequency roughness such as an irregular edge surface (as shown in FIG. 1C). In reality, the LWR is a combination of the high-frequency LWR and the low-frequency LWR. The LWR is a measure of how smooth the edge of a linear feature is when viewed from the top down. Features with high LWR are generally very undesirable because the CD measured along the line feature would vary from position to position, rendering operation of the resulting device unreliable.